library verilog;
use verilog.vl_types.all;
entity dti_asym_tb is
    generic(
        IN_WIDTH        : integer := 24;
        OUT_WIDTH       : integer := 8;
        BYTE_ORDER      : integer := 1;
        ERR_MODE        : integer := 1
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of IN_WIDTH : constant is 1;
    attribute mti_svvh_generic_type of OUT_WIDTH : constant is 1;
    attribute mti_svvh_generic_type of BYTE_ORDER : constant is 1;
    attribute mti_svvh_generic_type of ERR_MODE : constant is 1;
end dti_asym_tb;
